FIG. 1 is a simplified block diagram of a multibit sigma-delta analog-to digital converter 10 of a type generally known in the art, which includes correction of static nonlinearities introduced by a multibit DAC in the sigma-delta (.SIGMA..DELTA.) feedback loop. The correction of FIG. 1 results in significant reduction in passband DAC errors, given sigma-delta converters using low clock rates and narrow bandwidths (clock rates of about 5 MHz and bandwidths less than about 100 KHz at the current state of the art). Increased- or high-bandwidth sigma-delta converters use higher clock rates and wider bandwidths (clock rates of 500 MHz to 3.3 GHz, and bandwidths of 10 MHz to 100 MHz, at the present state of the art), and noise shaping bands centered at carriers such as 70 MHz to 1 GHz, at the present state of the art. The high-speed DACs used in such high-bandwidth sigma-delta loops will introduce error terms which result both from static and dynamic nonlinearities. The dynamic nonlinearities which account for mismatches in rise and fall times and overall delay skew between DAC levels differ from static nonlinearities, which account for only amplitude errors. The dynamic error is generally the dominant error term in high-speed multibit sigma-delta analog-to-digital converters. Therefore, multibit sigma-delta error correction capable of correction of dynamic nonlinearities would be advantageous.
In the arrangement of FIG. 1, analog input signals applied to an analog input port 12 are summed in a summing circuit 14 with correction signals applied to an input port 142 from a signal path 24. The summed analog and correction signals are applied from summing circuit 14 to an input port 16i of a baseband multibit signal-delta modulator 16. Parallel sampled binary digital signals representing the analog input signals applied to input port 16i are produced at output port 16o. The digital signals at output port 16o are applied to the address input ports of a programmable ROM and to a static DC level calibrator 20. PROM 18 is preprogrammed at each memory location with error correction values established by the static DC level calibrator 20, for producing corrected signals y(n) at its output port 18o. Averaging circuit 20 receives the parallel sampled binary digital signals y(n) from output port 16o and averages or integrates the samples in an averager 22 by summation over a large number of samples, such as for example one thousand or more samples. The parenthetical expression (n) in the expression y(n) represents the index number of each of the samples. The averaging in block 20 removes quantization noise produced by the baseband multibit sigma-delta (.SIGMA.-.DELTA.) modulator 16. The averaged samples are applied to level calibrator 20, which, at initial turn-on, or during a calibration procedure, produces a known direct level, such as a direct voltage or bias, which is applied over a signal path 24 to input port 14i of summing circuit 14, for addition or injection of the direct level for measuring direct (DC) offsets at the output of multibit sigma-delta modulator 16. The DC calibrator will inject a direct level corresponding to each of the multibit quantization levels. The averager provides measured offsets for each of these levels. These measured offsets are subtracted from the corresponding level values, to produce look-up table values which compensate for the offsets when applied to PROM 18. Static DC level calibrator 22 also produces signals which program the memory locations according to this table. After the initialization or calibration period, the static DC level calibrator becomes inactive. In operation of the analog-to-digital converter 10 of FIG. 1, PROM 18 removes error introduced into the passband of the sigma-delta modulator 16 produced by the multibit digital-to-analog converter inherent therein.
As so far described, the arrangement of FIG. 1 is that of a known analog-to-digital converter. It should be noted that the PROM 18 and feedback calibrator 22 correct only baseband nonlinearity errors produced by static or constant gain mismatches inherent in the sigma-delta modulator, because averager 20 can only detect direct bias errors occurring at or near zero Hz.
In order to more fully explain the sources of the errors in sigma-delta modulator 16, a sigma-delta modulator is illustrated within block 16. The particular sigma-delta modulator which is illustrated is the multibit .SIGMA.-.DELTA. modulator with static error correction which is described in M. Nejad & G. Temes, "Multibit Oversampled Sigma-Delta A/D Converter with Digital Error Correction," published at pp. 1051-1052 in Vol. 24 of IEEE Electronics Letters, June 1993. The arrangement of FIG. 1 illustrates the Nejad et al. converter within block 16.
In FIG. 1, analog-to-digital converter 16 includes a first summing circuit 30 which has a noninverting (+) input port 30.sub.1 coupled to the output port of summing circuit 14, and an inverting (-) input port 302 coupled for receiving, from a feedback signal path 41b, feedback signal in the form of reconstructed analog signal. First summing circuit 30 subtracts the reconstructed analog signal from the analog input signal applied to input port 16i, to generate a .DELTA.(t) signal. The .DELTA.(t) signal is applied through an additional theoretical or hypothetical summing circuit 32 to an input port of an integrating loop filter 34. Hypothetical summing circuit 32 is considered to be the location at which equivalent input loop filter noise .eta.(t) of the following circuits is added to the .DELTA.(t) signal.
Integrating loop filter 34 integrates the delta signal from hypothetical summing circuit 32, to produce integrated signals u(t) at its output port. The integrating loop filter 34 has poles place near zero Hz for producing frequency selective gain in the passband of the sigma-delta modulator, which is centered at zero Hz. In order to have gain, the loop filter 34 is preferably an active filter. The filtered signals u(t) at the output port of filter 34 are applied to a multibit analog-to-digital converter illustrated as a block 36, which operates at the frequency f.sub.s of a clock signal applied over a signal path 37. Block 36 includes a further hypothetical noise source illustrated as a summing circuit 38, which adds to the digitized output signal a noise component which can be termed ADC quantization noise or equivalent error signals e(n), which includes quantization noise. The digitized (discrete in both time and level) output signals from ADC 36 are applied as an output signal to output port 16o of sigma-delta modulator 16, and within sigma-delta modulator 16, are applied over a feedback signal path 41a of a feedback loop 39 to a digital-to-analog converter illustrated as a block 40.
Within feedback loop 39, DAC 40 converts the digitized signal from the output port of ADC 36 into the reconstructed analog signal at the clock frequency f.sub.s, and applies the resulting converted signal over a signal path 41b of feedback loop 39 to the inverting input port 30.sub.2 of summing circuit 30. As illustrated in FIG. 1, DAC 40 also includes a further hypothetical summing circuit 42, which adds an equivalent error signal, produced by nonlinearity of the ADC 40, to the converted output signal. As suggested by dotted line 44, the ADC 36 and DAC 40 are often a part of a common integrated circuit.
It should be noted that for simplicity of design and operation, ADC 36 and DAC 40 may use specialized forms of coding, such as binary, thermometer, and level. The coupling between ADC 36 and output port 26o of multibit analog-to-digital converter 16 often includes a code converter, illustrated as 17, for converting the code used internally between ADC 36 and DAC 40 into ordinary digital code at output port 16o.
In the arrangement of FIG. 1, sigma-delta modulator 16 processes noise over its passband produced by nonlinearity in the DAC 40, which, at the output of the ADC 36, tends to be larger than the shaped quantization noise characterized as the ADC quantization noise e(n), attenuated by the noise transfer function of the sigma-delta modulator over the passband. The nonlinearity noise g(t) is not attenuated by the sigma-delta loop, and so tends to limit the dynamic range of the ADC 16. PROM 18 and static dc level calibrator 22 are provided in the prior art to ameliorate the effect of the nonlinearities produced by DAC 40 by at least partial cancellation or reduction of noise.
Improved analog-to-digital sigma-delta converters are desired.